Semiconductor memories, such as static random access memory (SRAM) or dynamic random access memory (DRAM), have large number of memory cells arranged in arrays. A particular memory cell inside an array is typically selected by a wordline and a pair of bitlines. The wordline is typically connected to one or more control gates of every memory cell in a row. In case the control gates are made of NMOS transistors, all the memory cells are turned on when the wordline connected thereto turns to a high voltage, i.e., to be activated. The bitline pair is typically connected to storage nodes of every memory cell in a column to a sense amplifier. The memory cell at the cross point of the activated wordline and the bitline pair is the one that is selected.
In a modern high density semiconductor memory, the wordline may be very long, especially when the word width becomes very large. The wordline has to be formed inevitably by one or more metal layers. Even so, delays caused by long wordline's resistance and capacitance pose performance limitations and reliability problems in such high density semiconductor memory. Especially with the advances of process technologies which shrink down metal width and thickness, the wordline's resistance becomes very significant in comparison with a drive transistor's channel resistance. For instance, for a wordline being connected to 256 cells, when in a 65 nm technology, the wordline resistance is about 300 ohm; but when in a nm 45 nm technology, the wordline resistance is 1027 ohm. At the same time, for a driver's PMOS transistor with a channel width of 10 um, when in a 65 nm technology, the channel resistance is 259 ohm; but when in a 45 nm technology, the channel resistance is 189 ohm. As a result, the ratio between wire resistance and transistor channel resistance drastically increases when technology advances. The higher ratio increases wordline slew time, which reduces effective wordline pulse width and degrades read/write margin or even causes malfunctions.